Computer Architecture
RISC vs CISC: The Architecture Wars
Цели урока
- Understand the philosophy and history of CISC
- Know CISC's problems for pipelining
- Understand the principles of RISC architecture
- Know the key RISC processors
- Understand the hybrid approach of modern CPUs
Предварительные знания
- Instruction cycle
- Pipelining
Your iPhone on an ARM processor outperforms a laptop with Intel? The story of how 'less' became 'faster'.
- Apple Silicon (M1, M2, M3) - ARM conquers the desktop
- RISC-V in IoT and embedded systems
- ARM servers (AWS Graviton, Ampere)
- x86 in data centers and legacy systems
History of the conflict
1977: VAX-11 - the pinnacle of CISC, 300+ instructions. 1980: Patterson & Hennessy begin RISC research at Berkeley and Stanford. 1984: MIPS R2000 - first commercial RISC. 1985: ARM1 - beginning of ARM (Acorn RISC Machine). 1989: Intel 486 - RISC core inside x86. 2007: iPhone - ARM in every pocket. 2010: RISC-V - open standard. 2020: Apple M1 - ARM on the desktop beats Intel.
CISC: Making Life Easier for Programmers
**1970s:** Memory is expensive, compilers are primitive, programmers write in assembly. The solution? Powerful instructions!
**CISC (Complex Instruction Set Computer):** One instruction does a lot of work. Less code = less memory.
| CISC feature | Example (x86) | Purpose |
|---|---|---|
| Complex addressing modes | MOV EAX, [EBX+ECX*4+8] | Access to arrays of structs |
| Variable-length instructions | 1-15 bytes | Memory savings |
| Many special instructions | ENTER, LEAVE, LOOP | Common code patterns |
| Microcode | Internal interpreter | Complex operations |
**VAX-11 (1977):** 300+ instructions! Including POLY for polynomial evaluation and INDEX for array bounds checking.
The main goal of CISC in the 1970s:
Problems with CISC
**1980s:** Research by Patterson and Hennessy revealed - complex instructions are rarely used!
**CISC problems for pipelining:**
| Problem | Why | Consequences |
|---|---|---|
| Variable instruction length | Requires a complex decoder | Non-parallel fetch |
| Variable execution time | ADD = 1 cycle, DIV = 40 | Stalls the entire pipeline |
| Memory operands | CISC: ADD [mem], reg | Unpredictable latency |
| Microcode | Internal loop | Occupies the pipeline |
**The CISC irony:** 1980s compilers became smarter and stopped using complex instructions - simple ones are faster!
The main problem with CISC for pipelining:
RISC: Less Means Faster
**RISC (Reduced Instruction Set Computer):** Simple instructions, but FAST. Move complexity to the compiler.
**Paradox:** More instructions, but fewer cycles. Why?
| Factor | CISC | RISC |
|---|---|---|
| Instructions per task | Fewer | More (~30%) |
| Cycles per instruction | 3-10 (CPI) | ~1 (CPI) |
| Clock frequency | Limited by complexity | Higher |
| Total | CPI × instructions | Less! |
**Formula:** Time = Instructions × CPI × Cycle period. RISC wins in the product!
Load/Store architecture means:
RISC Design Principles
**Key RISC design decisions:**
**RISC-V:** Open RISC ISA (2010). Base set - 47 instructions. Modular extensions (M, A, F, D, C).
If MIPS has 32 registers, how many bits are needed to encode one register number?
RISC Processors: MIPS, ARM, RISC-V
**MIPS (1984):** First commercially successful RISC. PlayStation 1/2, networking equipment.
**ARM (1985):** Low power consumption. Mobile devices, 200+ billion chips produced.
**RISC-V (2010):** Open standard, free license. The future of RISC.
| RISC ISA | Registers | Bits | Notable features |
|---|---|---|---|
| MIPS | 32 | 32/64 | Classic textbook RISC |
| ARM | 16/31 | 32/64 | Conditional instructions, Thumb |
| RISC-V | 32 | 32/64/128 | Modular, open standard |
**ARM Thumb:** 16-bit instructions for code density. A compromise between RISC purity and size.
A unique feature of the ARM architecture:
The Present: A Hybrid Approach
**War outcome:** Nobody won. Modern processors are hybrids!
**Apple M1 (ARM):** Pure RISC, but with massive OoO and predictors. The best of both worlds.
| Aspect | x86 (Intel/AMD) | ARM (Apple M1/Qualcomm) |
|---|---|---|
| ISA | CISC (externally) | RISC |
| Decoder | Complex, expensive | Simple, efficient |
| Decode energy | ~15% of core power | ~5% of core power |
| Compatibility | 40 years of software | Requires recompilation |
| Code density | Better (variable length) | Worse (fixed 32 bits) |
| Performance/Watt | Worse | Better |
**ARM on the desktop:** Apple M1 showed that ARM can compete with x86 in performance. Windows on ARM is growing.
RISC is always faster than CISC
Modern x86 processors internally use RISC-like micro-operations and are extremely fast.
Implementation matters, not just ISA. x86 with trillions of dollars of investment is optimized to the limit.
Why does x86 still dominate on desktops?
Key Ideas
- CISC: complex instructions to save memory (1970s)
- Problem: complex instructions pipeline poorly
- RISC: simple instructions, 1 cycle, many registers
- Load/Store: arithmetic only on registers
- Modern x86 internally translates to RISC μops
- ARM dominates mobile, growing on desktop
- RISC-V - the open future
Related Topics
RISC/CISC is the foundation for understanding modern processors.
- Pipelining — RISC is optimized for pipelines
- ARM and x86 — Concrete implementations